Input-output buffers may be used to send or receive signals to or from a communication line. For example, in a data processing system, a processor may send signals over a bus by way of a buffer. As system operating speeds increase, the impedance presented by the buffer may affect the integrity of communications on the bus.
Additionally, signals of a bus within a data processing system may comprise voltage levels different from those within (e.g., within the core of) an integrated circuit. For example, in some applications, a bus may be transferring signals between devices, e.g., a processor and memory, that are unrelated to a secondary integrated circuit, e.g., of a printer interface, that may be coupled thereto. In such application, a buffer of the secondary integrated circuit might be disabled or tri-stated while not actively communicating over the bus. However, if signal levels on the bus may exceed voltages of the integrated circuit, its isolation from the bus may be affected.
To adjust an output impedance of a buffer, a resistive legging/ladder structure might be formed in series with a driver transistor coupled to the output node. Based upon a determined resistance or I-V characteristic of the drive transistor, the resistive legging structure may be structured to contribute a predetermined compensation resistance. Accordingly, the drive transistor may present, in combination with the structured resistive legging circuit, an impedance suitable for interfacing the bus.
More recently, manufacturers have been seeking additional measures to enhance system operating speeds while preserving bus integrities and maintaining the reliability of integrated circuits.